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0001-Update-LoongArch-Vol1-EN-to-v1.10-part2.patch
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0001-Update-LoongArch-Vol1-EN-to-v1.10-part2.patch
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From 2c991a0b7edbf91b94039bdf8af959f7763cc67d Mon Sep 17 00:00:00 2001
From: Yanteng <siyanteng@loongson.cn>
Date: Thu, 11 Apr 2024 19:38:46 +0800
Subject: [PATCH] Update LoongArch-Vol1-EN to v1.10 part2
add message interrupt.
add some inst.
fix cover lettrt.
Signed-off-by: Yanteng <siyanteng@loongson.cn>
---
LoongArch-Vol1-EN.adoc | 2 +-
.../other-miscellaneous-instructions.adoc | 50 ++++++++++++++++---
.../exceptions-and-interrupts.adoc | 2 +
.../message-interrupts.adoc | 10 ++++
.../message-interrupt-entry.adoc | 4 ++
.../message-interrupt-priority.adoc | 8 +++
...message-interrupt-response-processing.adoc | 6 +++
.../message-interrupt-types.adoc | 6 +++
docs/LoongArch-Vol1-EN/introduction.adoc | 2 +
.../introduction/version-evolution.adoc | 6 +++
.../new-in-loongarch-v1.1.adoc | 24 +++++++++
11 files changed, 113 insertions(+), 7 deletions(-)
create mode 100644 docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts.adoc
create mode 100644 docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-entry.adoc
create mode 100644 docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-priority.adoc
create mode 100644 docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-response-processing.adoc
create mode 100644 docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-types.adoc
create mode 100644 docs/LoongArch-Vol1-EN/introduction/version-evolution.adoc
create mode 100644 docs/LoongArch-Vol1-EN/introduction/version-evolution/new-in-loongarch-v1.1.adoc
diff --git a/LoongArch-Vol1-EN.adoc b/LoongArch-Vol1-EN.adoc
index 0112a03..1e3103b 100644
--- a/LoongArch-Vol1-EN.adoc
+++ b/LoongArch-Vol1-EN.adoc
@@ -1,6 +1,6 @@
= LoongArch Reference Manual - Volume 1: Basic Architecture
Loongson Technology Corporation Limited
-v1.00
+v1.1
:title-separator: -
:docinfodir: themes
:docinfo: shared
diff --git a/docs/LoongArch-Vol1-EN/basic-integer-instructions/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc b/docs/LoongArch-Vol1-EN/basic-integer-instructions/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc
index 6281620..65f63b6 100644
--- a/docs/LoongArch-Vol1-EN/basic-integer-instructions/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc
+++ b/docs/LoongArch-Vol1-EN/basic-integer-instructions/overview-of-basic-integer-instructions/other-miscellaneous-instructions.adoc
@@ -150,8 +150,8 @@ The undefined field in the defined configuration word can be read back to any va
|`1` indicates support for page attributes of huge page
^m|25
-^m|IOCSR_BRD
-|`1` indicates that the string of processor product information is recorded at address `0` of the IOCSR access space
+^m|CRC
+|`1` indicates that support CRC instruction
That is, information such as "`Loongson3A5000 @ 2.5GHz`"
@@ -159,7 +159,7 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
^m|MSG_INT
|`1` indicates that the external interrupt uses the message interrupt mode, otherwise it is the level interrupt line mode
-.17+^m|2
+.24+^m|2
^m|0
^m|FP
|`1` indicates support for basic floating-point instructions
@@ -231,7 +231,37 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
^m|LAM
|`1` indicates support `AM*` atomic memory access instruction
-.12+^m|3
+^m|24
+^m|HPTW
+|`1` indicates support Page Table Walker
+
+^m|25
+^m|FRECIPE
+|`1` indicates support FRECIPE.{S/D}、FRSQRTE.{S/D}.
+If 128-bit vector extension is also supported, VFRECIPE.{S/D}、VFRSQRTE.{S/D} is supported.
+If 256-bit vector extension is also supported, XVFRECIPE.{S/D}、XVFRSQRTE.{S/D} is supported.
+
+^m|26
+^m|DIV32
+|`1` indicates that DIV.W[U] and MOD.W[U] instructions on 64-bit machines compute only the low 32-bit data of the input register
+
+^m|27
+^m|LAM_BH
+|`1` indicates support AM{SWAP/ADD}[_DB].{B/H}.
+
+^m|28
+^m|LAMCAS
+|`1` indicates support AMCAS[_DB].{B/H/W/D}.
+
+^m|29
+^m|LLACQ_SCREL
+|`1` indicates support LLACQ.{W/D}、SCREL.{W/D}.
+
+^m|30
+^m|SCQ
+|`1` indicates support SC.Q.
+
+.14+^m|3
^m|0
^m|CCDMA
|`1` indicates support for hardware Cache coherent DMA
@@ -257,11 +287,11 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
|`1` indicates support LL automatic with dbar function
^m|6
-^m|ITLBT
+^m|ITLBTHMC
|`1` indicates that the hardware maintains the consistency between ITLB and TLB
^m|7
-^m|ICACHET
+^m|ICHMC
|`1` indicates that the hardware maintains the data consistency between ICache and DCache in one processor core
^m|10:8
@@ -280,6 +310,14 @@ That is, information such as "`Loongson3A5000 @ 2.5GHz`"
^m|RVAMAX-1
|The maximum configurable virtual address is shortened by `-1`
+^m|17
+^m|DBAR_hints
+|1 indicates that the non-0 value of the DBAR is implemented according to the recommended meaning of the manual.
+
+^m|23
+^m|LD_SEQ_SA
+|1 indicates that the hardware is enabled to guarantee sequential execution of load operations at the same address.
+
^m|4
^m|31:0
^m|CC_FREQ
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts.adoc
index 73e9be0..4286647 100644
--- a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts.adoc
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts.adoc
@@ -3,6 +3,8 @@
include::exceptions-and-interrupts/interrupts.adoc[]
+include::exceptions-and-interrupts/message-interrupts.adoc[]
+
include::exceptions-and-interrupts/exceptions.adoc[]
include::exceptions-and-interrupts/reset.adoc[]
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts.adoc
new file mode 100644
index 0000000..dedbdfa
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts.adoc
@@ -0,0 +1,10 @@
+[[message-interrupts]]
+=== Message-Interrupts
+
+include::message-interrupts/message-interrupt-types.adoc[]
+
+include::message-interrupts/message-interrupt-priority.adoc[]
+
+include::message-interrupts/message-interrupt-entry.adoc[]
+
+include::message-interrupts/message-interrupt-response-processing.adoc[]
\ No newline at end of file
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-entry.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-entry.adoc
new file mode 100644
index 0000000..f6c03e1
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-entry.adoc
@@ -0,0 +1,4 @@
+[[message-interrupt-entry]]
+==== Message-Interrupt-Entry
+
+All message interrupts adopt a uniform entry, and the "entry page number" of their computed entry address coincides with the line interrupt, coming from an "in-page offset" equal to 2(CSR.ECFG.VS+2)×78(0x4E) of their computed entry address.
\ No newline at end of file
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-priority.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-priority.adoc
new file mode 100644
index 0000000..2fb00b0
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-priority.adoc
@@ -0,0 +1,8 @@
+[[message-interrupt-priority]]
+==== Message-Interrupt-Priority
+
+Loongson architecture adopts a fixed priority among 256 message interrupts in each logical processor core. The larger the interrupt number, the higher the priority, that is, message number 255 has the highest priority, message number 254 has the second,...... , message 0 has the lowest interrupt priority.
+
+Only message interrupts recorded inside each logical processor core whose priority is not lower than the message interrupt enable priority threshold (recorded in the CSR.MSGIE.PT field) can be further selected and set by the hardware.
+
+When there are both message interrupt request and line interrupt request in a processor core, the message interrupt request has higher priority than the line interrupt request.
\ No newline at end of file
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-response-processing.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-response-processing.adoc
new file mode 100644
index 0000000..e5af6d5
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-response-processing.adoc
@@ -0,0 +1,6 @@
+[[message-interrupt-response-processing]]
+==== Message-Interrupt-Response-Processing
+
+When the message interrupt is routed to the specified processor core, the processor core will set the corresponding status position of internal CSR.MSGIS0~CSR.MSGIS3 to 1 according to the interrupt number, and this process is recorded for the message interrupt. Then the processor core selects the interrupt with the highest priority among the recorded message interrupts whose interrupt number is not lower than the message interrupt enable priority threshold (recorded in the CSR.MSGIE.PT field), and records its message interrupt number in the CSR.MSGOR.INTNUM field, and sets the CSR.MSGOR.NULL bit to zero CSR.ESTAT.MSGINT position 1, this process picks and sets the message interrupt request for the message interrupt. When the CSR.ESTAT.MSGINT bit is 1, only the global interrupt enables CSR.CRMD.IE to block the message interrupt requests that are picked and set.
+
+In the case that the CSR.ESTAT.MsgInt bit is 1, if the software reads the CSR.MSGIR register, the hardware will automatically clear the corresponding status of CSR.MSGIS0 to CSR.MSGIS3 according to the message interrupt number currently recorded in the CSR.MSGIR.INTUM field 0. If there is no more selected message interrupt in CSR.MSGIS0~CSR.MSGIS3 after the interrupt status bit of this message is cleared 0, the CSR.ESTAT.MSGINT bit will be cleared 0 by the hardware and CSR.MSGIR.NULL position 1 in the next processor core internal clock cycle. Software developers are especially reminded that because of the "read clear" nature of the CSR.MSGIR register, it is recommended to read the CSR.ESTAT.MSGINT bits when checking for pending message interrupts.
\ No newline at end of file
diff --git a/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-types.adoc b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-types.adoc
new file mode 100644
index 0000000..b7c2337
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/exceptions-and-interrupts/message-interrupts/message-interrupt-types.adoc
@@ -0,0 +1,6 @@
+[[message-interrupt-types]]
+==== Message-Interrupt Types
+
+In the Loongson architecture, 256 message interrupts can be recorded inside each logical processor core, which can include message-type intercore interrupts and message-type hard interrupts input from outside the processor core.
+Within a processor core, four 64-bit CSRS, CSR.MSGIS0 to CSR.MSGIS3, record in turn whether messages from 0 to 255 are interrupted or not.
+The exact source of the 256 message interrupts inside each processor core is determined by the implementation, and software developers need to refer to the specific chip user manual for information.
\ No newline at end of file
diff --git a/docs/LoongArch-Vol1-EN/introduction.adoc b/docs/LoongArch-Vol1-EN/introduction.adoc
index 54af609..5f41081 100644
--- a/docs/LoongArch-Vol1-EN/introduction.adoc
+++ b/docs/LoongArch-Vol1-EN/introduction.adoc
@@ -12,3 +12,5 @@ include::introduction/instruction-formats.adoc[]
include::introduction/assembly-instruction-mnemonic-formats.adoc[]
include::introduction/conventions-used-in-this-manual.adoc[]
+
+include::introduction/version-evolution.adoc[]
diff --git a/docs/LoongArch-Vol1-EN/introduction/version-evolution.adoc b/docs/LoongArch-Vol1-EN/introduction/version-evolution.adoc
new file mode 100644
index 0000000..cb6ee3c
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/introduction/version-evolution.adoc
@@ -0,0 +1,6 @@
+[[version-evolution]]
+=== Version Evolution
+
+The initial version of LoongArch is V1, denoted as LoongArch V1. The content of the standard is not specified in the LoongArch Reference Manual and belongs to LoongArch V1 by default. Since LoongArch V1, the subsequent evolution of LoongArch adopts the method of fine-grained incremental evolution. By "fine-grained" evolution, I mean that each subset of functionality in the base or extensions can evolve independently; By "incremental" I mean that a higher version is always compatible with the previous binary for any part that can be evolved independently. In order to more concisely reflect the stages of the above architecture evolution process, a number of new feature subset extensions added in a certain stage are collectively referred to as a new version extension. For example, the new hardware page table traversal support, byte/half-word atomic memory access instructions, and other additions to LoongArch V1 are collectively referred to as LoongArch V1.1. It should be pointed out that the subset of features added in each new version has its own identifier in the CPUCFG instruction return value. It is recommended that the software use this information rather than the version number of the Godson architecture to determine the supported features of the running processor. Architecture specifications do not require processor hardware to implement functions that directly reflect the supported architecture version number.
+
+include::version-evolution/new-in-loongarch-v1.1.adoc[]
diff --git a/docs/LoongArch-Vol1-EN/introduction/version-evolution/new-in-loongarch-v1.1.adoc b/docs/LoongArch-Vol1-EN/introduction/version-evolution/new-in-loongarch-v1.1.adoc
new file mode 100644
index 0000000..b20c83a
--- /dev/null
+++ b/docs/LoongArch-Vol1-EN/introduction/version-evolution/new-in-loongarch-v1.1.adoc
@@ -0,0 +1,24 @@
+[[new-in-loongarch-v1.1]]
+==== New In LoongArch V1.1
+
+LoongArch V1.1 adds the following:
+
+1. New instructions for approximately solving floating-point root and inverse floating-point root, including FRECIPE.S, FRECIPE.D, FRSQRTE.S, FRSQRTE.D for scalar operations. VFRECIPE.S, VFRECIPE.D, VFRSQRTE.S, VFRSQRTE.D commands for 128-bit SIMD operations and XVFRECIPE.S, XVFRECIPE.D, XVFRSQRTE.S, XVFRSQRTE.D commands for 256-bit SIMD operations instructions.
+
+2. Add SC.Q instruction.
+
+3. Add LLACQ.W, SCREL.W, LLACQ.D, SCREL instructions.
+
+4. Add AMCAS.B, AMCAS.H, AMCAS.W, AMCAS.D, AMCAS_DB.B, AMCAS_DB.H, AMCAS_DB.W, AMCAS_DB.D, AMSWAP.B, AMSWAP.H instructions.
+
+5. Add AMADD.B, AMADD.H, AMSWAP_DB.B, AMSWAP_DB.H, AMADD_DB.B, AMADD_DB.H instructions.
+
+6. Add the function definition of non-zero hint value in the dbar instruction part.
+
+7. A new method for determining whether 32-bit integer division instructions on 64-bit machines are affected by the higher 32-bit value of the source operand register.
+
+8. Standardize the way to determine the sequential execution behavior of load memory access operations at the same address.
+
+9. Add the definition of a message interrupt.
+
+10. Hardware page table traversals are allowed.
\ No newline at end of file
--
2.44.0